This invention is related to the packaging of electronics devices and in particular, to a heat dissipation system for semiconductor integrated circuits. Semiconductor integrated circuit devices, such as chips and dies, are small in size and are designed to handle large amounts of power. A standing requirement in the packaging of integrated circuits is to provide, to the extent possible, maximum chip density to decrease conductor lengths. The resultant higher power levels which are used have a co-commitment requirement that the heat which is generated be effectively dissipated. This in turn has led to the use of a variety of heat dissipaters known as heat sinks. Such are required to achieve thermal stability for the integrated circuit.
Prior art techniques have been so large, heavy and expensive that in many cases the heat sinks more than offset the space and weight advantages which are gained by the use of integrated circuit devices. Prior art packaging techniques to achieve dissipation have followed a variety of alternative paths. One known technique is to have an integrated circuit mounted on a metallic strip of heat sink material. The chip and its heat sink mount are then encased in a dielectric casing with the metallic strip extending through the casing at various points and functioning as a conductive heat dissipation tab. The casing itself may be plastic or ceramic or another suitable dielectric material. This eliminates the use of a metal housing which is more costly. Such devices however present problems in not providing sufficient external surface area in which to provide effective heat dissipation. Additionally, the problem of physical attachment of the semiconductor device to the heat sink presents an additional problem. For example if a screw mount technique is used then a torque limiting tool may be required to ensure that the screw is tight enough to prevent shifting yet not be so tight as to break the plastic casing. An example of such packaging is illustrated in U.S. Pat. No. 3,670,215 having a chip mounted to a strip with the strip then extending through the package. A significant problem with such a system is the high cost and low through-put of fabrication. Consequently, while effective as a technique of heat dissipation, the increased cost and complexity of fabrication make it commercially unattractive. Moreover, the package itself may be weakened by the increased percentage of metal which passes through that housing.
U.S. Pat. No. 3,783,345 while not strictly applicable to integrated circuits illustrates the use of a single diode die and a thyrector, for the purpose of eliminating voltage spikes and achieving wrong polarity protection. In the '345 patent heat passes through a plastic matrix so there is no direct metal contact between the semiconductor element and the heat sink. That is, heat transfer is effectuated through the encapsulate material, a resin. This is a common problem in the prior art, that is, the molded body is a poor conductor of heat. U.S. Pat. No. 4,538,168 discloses an opposite technique for providing thermal dissipation in single diode dies. Again, while not applicable to integrated circuit chip fabrication since no lead frame is used or contemplated, a metal extruded carrier is employed with the diode encapsulated or potted on three sides. The high cost and low through-put fabrication of such devices makes them economically unsuitable for use with integrated circuit systems.
Heat sink techniques for use with single transistors for example, to provide alignment of carrier strips or to prevent peel, are disclosed in U.S. Pat. Nos. 3,418,089 and 4,107,727. Such systems do not employ lead frame technology and are not applicable for use in integrated circuit packaging techniques. An example of a chip carrier which encapsulates to provide heat dissipation is disclosed in U.S. Pat. No. 4,147,889. Heat dissipation in this system occurs through a glass epoxy or insulator material thereby lowering heat dissipation effectiveness. The system also requires many folding and bending steps thereby raising the cost and making it not applicable to situations where high through-put fabrication is required to lower the overall cost of the integrated circuit package.